Senior Mixed-Signal Logic Design Engineer and Architect (m/w/d)

Job title:

Senior Mixed-Signal Logic Design Engineer and Architect (m/w/d)

Company

Intel

Job description

Job Details:Job Description:Are you passionate about cutting-edge technology and innovation? Join our dynamic team as a Mixed-Signal and Digital Design Engineer, where you will play a pivotal role in developing high-performance IPs for next-generation products. This is an exciting opportunity to work on complex designs and collaborate with industry experts to push the boundaries of technology.Why Join Us?

• Innovative Projects: Work on groundbreaking projects that shape the future of technology.
• Collaborative Environment: Join a team of talented professionals who are passionate about innovation and excellence.
• Career Growth: Opportunities for continuous learning and professional development.
• Impactful Work: Contribute to the development of high-performance IPs that power next-generation products

Key Responsibilities

• Logic Design and RTL Coding: Develop the logic design, register transfer level (RTL) coding, and simulation for mixed-signal and high-speed IPs.
• Architecture Definition: Participate in defining architecture and microarchitecture features of the blocks being designed.
• Mixed-Signal Design: Apply various strategies, tools, and methods for mixed-signal designs, including analog behavior modeling and circuit simulation.
• Verification and Validation: Review verification plans and implementations to ensure design features are verified correctly. Resolve and implement corrective measures for failing RTL tests.
• Customer Support: Support SoC customers to ensure high-quality integration of the IP block.

Qualifications:

• Educational Background: Master’s or PhD degree in a relevant field with a minimum of 8 years of experience in mixed-signal and digital design.
• Technical Expertise:

• Proficiency in mixed-signal design validation, layout analysis, and deep sub-micron technology.
• Strong skills in writing and analyzing Verilog code.
• Experience in defining pin positions and writing constraints for timing clean layouts.
• Knowledge of DFT insertion steps and collaboration with DFT architects.
• Ability to generate timing libraries and structural models using SPEF extraction and SDF files.
• Understanding of clock domain crossings (Hyperscale and Spyglass).
• Proficiency in writing UPF files and using fusion compilers, with simulation experience in Synopsys VCS.

​This position is subject to the collective agreement for workers and employees in the electrical and electronics industry, employment group I. https://www.feei.at/wp-content/uploads/2024/04/caeei-2024-04-30.pdfPrior to entering an employment agreement, the employee will be asked to provide all documents and references to verify any service times of prior employment. Based on provided documents the appropriate number of service years will be credited as prior employmentJob Type: Experienced HireShift: Shift 1 (Austria)Primary Location: Austria, VillachAdditional Locations:Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC’s and critical IP’s sustain Intels Xeon and 5G networking roadmap.Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of Trust N/AWork Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Expected salary

Location

Villach, Kärnten

Job date

Wed, 19 Feb 2025 04:51:37 GMT

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